1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to semiconductor elements, such as substrate diodes, of SOI circuits formed in the crystalline material of the substrate.
2. Description of the Related Art
The fabrication of integrated circuits requires a large number of circuit elements, such as transistors and the like, to be formed on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed above a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of MOS transistors. Thus, the latter aspect renders the reduction of the channel length, and associated therewith the reduction of the channel resistivity, a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
In view of further enhancing performance of transistors, in addition to other advantages, the SOI (semiconductor or silicon on insulator) architecture has continuously been gaining in importance for manufacturing MOS transistors due to their characteristics of a reduced parasitic capacitance of the PN junctions, thereby allowing higher switching speeds compared to bulk transistors. In SOI transistors, the semiconductor region, in which the drain and source regions as well as the channel region are located, also referred to as the body, is dielectrically encapsulated. This configuration provides significant advantages, but also gives rise to a plurality of issues. Contrary to the body of bulk devices, which is electrically connected to the substrate, and thus applying a specified potential to the substrate maintains the bodies of bulk transistors at a specified potential, the body of SOI transistors is not connected to a specified reference potential, and, hence, the body's potential may usually float due to accumulating minority charge carriers, unless appropriate counter measures are taken.
A further issue in high performance devices, such as microprocessors and the like, is an efficient device internal temperature management due to the significant heat generation. Due to the reduced heat dissipation capability of SOI devices caused by the buried insulating layer, the corresponding sensing of the momentary temperature in SOI devices is of particular importance.
Typically, for thermal sensing applications, an appropriate diode structure may be used wherein the corresponding characteristic of the diode may permit information to be obtained on the thermal conditions in the vicinity of the diode structure. The sensitivity and the accuracy of the respective measurement data obtained on the basis of the diode structure may significantly depend on the diode characteristic, i.e., on the diode's current/voltage characteristic, which may depend on temperature and other parameters. For thermal sensing applications, it may, therefore, typically be desirable to provide a substantially “ideal” diode characteristic in order to provide the potential for precisely estimating the temperature conditions within the semiconductor device. In SOI devices, a corresponding diode structure, i.e., the respective PN junction, is frequently formed in the substrate material located below the buried insulating layer, above which is formed the “active” semiconductor layer used for forming therein the transistor elements. Thus, at least some additional process steps may be required, for instance, for etching through the semiconductor layer or a corresponding trench isolation area and through the buried insulating layer in order to expose the crystalline substrate material. On the other hand, the process flow for forming the substrate diode is typically designed so as to exhibit a high degree of compatibility with the process sequence for forming the actual circuit elements, such as the transistor structures, without undue negative effects on the actual circuit elements.
In other cases, other circuit elements may have to be formed in the crystalline substrate material on the basis of appropriately designed PN junctions, while not unduly contributing to overall process complexity. Hence, the circuit elements to be formed in the substrate material may typically be fabricated with a high degree of compatibility with the usual manufacturing sequence for the circuit elements formed in and above the actual semiconductor layer formed on the buried insulating material. For instance, typically, the PN junctions of the circuit elements in the crystalline substrate material may be formed on the basis of implantation processes, which are also performed in the actual semiconductor layer for forming deep drain and source regions, in order to provide an efficient overall manufacturing flow. In this case, an opening is typically formed so as to extend through the buried insulating layer and into the crystalline substrate material prior to performing the corresponding implantation process. Consequently, the dopant species may be introduced into the crystalline substrate material, i.e., into the portion exposed by the opening, so that corresponding PN junctions may be substantially aligned to the sidewalls of the opening, thereby also providing a certain “overlap” due to the nature of the implantation process and any subsequent anneal processes that may typically be required for activating the dopant species in the drain and source regions of the transistors and also to re-crystallize implantation-induced damage. However, during the further processing of the semiconductor device, for instance by performing appropriate wet chemical etch and cleaning processes, the lateral dimension of the opening may be increased due to an interaction with aggressive wet chemical etch chemistries, which may also have a significant influence on corresponding PN junctions formed in the crystalline substrate material, as will be described in more detail with reference to FIGS. 1a-1c. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in the form of an SOI device. The semiconductor device 100 comprises a substrate 101, which includes, at least in an upper portion thereof, a substantially crystalline substrate material 102, which may be pre-doped in accordance with device requirements. For example, the substrate material 102 may have incorporated therein an appropriate concentration of a P-type dopant and the like. In other cases, the crystalline substrate material 102 may comprise appropriately doped well regions as may be required for forming circuit elements, such as substrate diodes and the like. Furthermore, a buried silicon dioxide layer 103 (Box) is formed on the crystalline substrate material 102, followed by a semiconductor layer 104, typically provided in the form of a silicon layer, which may, however, also contain other components, such as germanium, carbon and the like, at least in certain device areas. For instance, the device 100 may comprise a first device region 110 and a second device region 120, wherein, in the first device region 110, one or more PN junctions 102P is provided in the crystalline substrate material 102, while, in the second device region 120, one or more circuit elements, such as transistors 121, are formed in and above the silicon layer 104. The PN junction 102P in the substrate material 102 may be substantially aligned to an opening 103A formed in the buried oxide layer 103 and also extending through the semiconductor layer 104, or any isolation region formed therein, depending on the overall device requirements.
Typically, the semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following processes. The substrate 101 may be provided so as to include the buried oxide layer 103 formed on the crystalline substrate material 102, while the semiconductor layer 104 is formed on the buried oxide layer 103, which may be accomplished on the basis of well-established wafer bond techniques, sophisticated implantation and oxidation processes and the like. Thereafter, isolation structures, such as shallow trench isolations (not shown), may be formed by using well-established lithography, etch, deposition and planarization techniques in order to obtain isolation trenches filled with an appropriate dielectric material, such as silicon dioxide. Thereafter, the basic dopant concentration in the corresponding active regions of the semiconductor layer 104 may be defined, for instance, by ion implantation and the like. Next, appropriate materials for a gate electrode structure 122 of the transistor 121 may be provided, for instance, by advanced oxidation and/or deposition techniques for providing an appropriate gate dielectric material, followed by the deposition of the gate electrode material, such as polysilicon and the like. On the basis of sophisticated lithography and etch techniques, the materials are patterned so as to obtain the gate electrode structure 122. Thereafter, appropriate implantation sequences may be performed in order to introduce a desired dopant concentration adjacent to the gate electrode structure 122, possibly on the basis of offset spacer elements (not shown). Thereafter, a sidewall spacer structure 123 is formed by well-established techniques, i.e., depositing an etch stop material (not shown) such as silicon dioxide, followed by the deposition of a silicon nitride material, which is then etched by anisotropic techniques in order to obtain the spacer structure 123. It should be appreciated that the spacer structure 123 may include two or more individual spacer elements, if a corresponding complex dopant profile may be required for drain and source regions 124 of the transistor 121. According to well-established process strategies, prior to defining the final dopant concentration of the drain and source regions 124, the opening 103A may be formed, which may be accomplished by appropriately covering the second device region 120 by an etch mask while defining the desired lateral size and position of the opening 103A in the first device region 110. Thereafter, an appropriate anisotropic etch process is performed, for instance, for etching through the semiconductor layer 104, if the opening 103A is to be formed through semiconductor material and the buried oxide layer 103, while, in other cases, when the opening 103A is enclosed by an isolation structure, the corresponding etch chemistry may be designed so as to etch through the dielectric material of the isolation structure and through the silicon dioxide material of the layer 103. After the etch process, the corresponding etch mask is removed and further processing is continued by performing an implantation process 105 in order to obtain the finally required dopant concentration for the drain and source regions 124. During the implantation process 105, the dopant species is introduced into the exposed portion of the substrate material 103 through the opening 103A so that a corresponding dopant concentration of the doped region 102B substantially corresponds to the dopant concentration of deep drain and source areas of the regions 124 of the transistor 121. Thereafter, typically, appropriately designed anneal processes are performed in order to activate the dopant species and also re-crystallize implantation-induced damage. Due to the nature of the implantation process 105 and due to the subsequent anneal processes, the PN junction 102P may be driven under the buried oxide layer 103, as indicated by the dashed line, wherein the degree of overlap of the layer 103 and the doped region 102B is determined by the process parameters of the previously-performed process sequence. Depending on the requirements for the dopant profile of the drain and source regions 124 of the transistor 121, a more or less pronounced degree of overlap may be created for the PN junctions 102P. Thereafter, further processing may be continued by performing further manufacturing steps as required for completing the basic transistor configuration. In particular, one or more sophisticated wet chemical cleaning or etch processes have to be performed in order to prepare exposed surface portions for the fabrication of a metal silicide in the drain and source regions 124 and possibly in the gate electrode structure 122.
FIG. 1b schematically illustrates the semiconductor device 100 during a corresponding wet chemical etch process 106, which is typically designed to remove oxide from exposed silicon surfaces in order to provide enhanced surface conditions during the subsequent silicidation process. Consequently, during the wet chemical process 106, exposed sidewall portions of the buried oxide layer 103 may be attacked and may be removed, thereby increasing the width of the opening 103A, as is indicated by the dashed lines. Consequently, the sidewalls 103S of the opening 103A, which previously acted as an implantation mask during the process 105 (FIG. 1a) thereby providing a desired dopant gradient at the PN junction 102P, may now expose a more or less pronounced portion of the doped region 102B, which may result in non-desirable characteristics of the PN junction or which may even result in a non-functional PN junction after the silicidation process.
FIG. 1c schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage, in which metal silicide regions 125 are formed in the transistor 121 and a corresponding metal silicide region 115 is formed in the doped region 102B. Due to the preceding material removal at the sidewalls 103S, the metal silicide 115 may significantly extend into the PN junction region 102P and may even result in a short circuit at critical regions 102C, thereby resulting in a complete failure of a corresponding circuit element that requires the operational PN junction 102P for proper operation. Even if the metal silicide region 115 does not extend across the PN junction 102P in the critical areas 102C, a significant modification of the junction characteristics may result, which may significantly affect performance of the corresponding device, for instance a substrate diode, which relies on a predictable diode characteristic, which in turn is based on the design of the PN junction 102P.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.